Analog in-memory computing attention mechanism for fast and energy-efficient large language models
Leroux, Manea, Sudarshan, Finkbeiner, Siegel, Strachan & Neftci
↗Engineer · PhD Researcher
Paul-Philipp
Manea
I develop novel computing architectures for AI, combining analog, in-memory and neuromorphic hardware to make intelligent systems faster and more sustainable.
01 / Publications
Selected writing
& research.
Gain Cell-Based Analog Content Addressable Memory for Dynamic Associative Tasks in AI
Manea, Leroux, Neftci & Strachan
↗Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories
Manea, Sudarshan, Cüppers & Strachan
↗Analog Feedback-Controlled Memristor Programming Circuit for Analog Content Addressable Memory
Yu, Manea, Ameli, Hizzani, Eldebiky & Strachan
↗02 / Projects
Hardware for
a smarter future.
Generative AI
In-memory attention for large language models
Gain-cell arrays store and process key-value data directly in memory, reducing the movement of data at the heart of Transformer inference.
Discover the work →Associative computing
Analog content-addressable memories
Circuit and architecture research into fast, energy-efficient associative search using CMOS and emerging memristive technologies.
Discover the work →Circuit research
Hardware–algorithm co-design
Connecting device non-idealities, analog circuit design and machine-learning models to build practical accelerators for sustainable AI.
My research profile →03 / Blog & notes
From the
research desk.
Building cimeda: an open-source workbench for IC design
Bringing schematics, simulation and layout into one place—and looking for co-founders to build it with me.
Open-source EDAIC designBuilding cimeda
Read the post →More from my research
AI
within
memory
within
memory
Why attention needs a different kind of memory
As language models grow, repeatedly moving their changing key-value cache becomes an energy and latency bottleneck. Gain cells offer a path to processing it where it is stored.
Read the paper →100×
faster
faster
Toward ultrafast, low-power generative AI
Our analog attention architecture demonstrates how circuit innovation and hardware-aware training can work together to retain model performance.
Read the preprint →04 / About me
Engineering
with purpose.
I am an engineer and PhD researcher at Forschungszentrum Jülich and RWTH Aachen University.
My research focuses on dedicated hardware for AI: neuromorphic and mixed CMOS–memristive technologies, analog content-addressable memories and in-memory computing. The goal is to reduce the energy footprint of increasingly capable AI systems.
Before my PhD, I developed electronics for space applications and worked on the DESTINY+ Dust Analyzer. In 2025, I joined Hewlett Packard Enterprise Labs as a research intern, designing and validating analog and in-memory computing circuits.